Constant Current Source - Back to the drawing Board

So, I'm right in the middle of moving. New digs, bigger house for the family and, as a bonus, a Garage with an apex roof! More storage, more room to tinker, its gonna be biblical!

Ask a question...

...get a different answer! Its a typical case of asking a question and then someone points out something else, opens a massive can of worms.

http://www.eevblog.com/forum/projects/i-should-know-this-but/

So this lead to some interesting research. Parallelling MOSFET's is not as straight forward as it seems...

The Issue

So compared to my original sec of the constant current driver, I was off target to reach a max current of 7A. It was turning out to be 5A. And although Parallelling MOSFET's was the right way of going about it, I was doing it wrong: http://www.ixys.com/Documents/Articles/Article_Linear_Power_MOSFETs.pdf

Because each FET does not have exactly the same R_DS or V_GTH. This effects the Drain current, I_D. This means that each FET will not pull exactly its equal share of current. This can cause a number of problems: One is one FET gets hotter and this changes the value of R_DS. But there are also 2 modes where the R_DS has positive and negative coefficients in the Linear region and the "fully on" region. For a constant current source, these MOSFETs will be working in the linear region, this means the the R_DS has a negative tempco and as temp goes up, R_DS goes down, more current flows, FET gets hotter and before you know it your MOSFET is smoke!

Take the proposed circuit above and the Total current I_t is 5A, therefore the voltage across the single shunt/source resistor R₁would be 5V for a 1OHM shunt. The same MOSFETs aren't always cut from the same die, as it were: Q1 could have an R_DS of 0.1OHMS at a V_GS of 3V and Q2 could have an R_DS of 0.105OHMS at the same V_GS. The data sheet does have these curves of R_DS Vs V_GS 

This means I₁ does not equal I₂, I₁ could be 0.5A and I₂ could be 4.5A, yet you'd still get the same voltage drop across the shunt resistor, R₁, the current is therefore unbalanced, Q2 bears most of the load and eventually, regardless of heatsinking, it goes pop!

Even if the datasheet say its bang on, if one FET is 1^oC warmer or cooler than the other, it could mean the difference between a few milliOHM's R_DS

Have a look at page 3. for the FDP6670AL -  it shows all the graphs.

Amongst other things Wong with the design: the LM324 was pointed out to be, well; a bit shit! Really bad offset voltage.

So how did I overcome these problems...?

Some Changes

First off; a better Op-amp: LT1014 - low voltage offset, same package and pinout as the LM324, and I have some in stock, perfect.

So that was easy, but now had to put thinking cap on about my FET array.

Instead of using 1 series shunt resistor and one Op-amp to do the control, I decided that 4 MOSFETS, each with a series shunt resistor and control op-amp.

As mentioned before though, someone will pick your design apart, and usually not in the area you asked your original question, you know: "you do know that...?" or "I'm surprised that works!"

Well that's exactly what happened, not that I'm ungrateful for it, far from it, ignoring criticism is a fatal mistake I find, that's if its constructive!

Seems my feedback network was somewhat thrown together (see Current Source Update for schematic): C8 & R18 on the output of U1:A are there to suppress some ringing on that output which showed itself on the load source, not desirable. So I just threw in a LP-RC filter and it got rid of it.

However I didn't measure the transient response, didn't even cross my mind to be honest. I referred back to the design I was taking my inspiration from and he had saw he had an RC in parallel in his feedback (R7 & C5). Possibly to compensate for the slow reaction time of the system to stabilise.

Someone else on the forum suggested that I reduce the output impedance of U1:A by using an emitter follower and that this would improve transient response too.

Only one thing for it: TO THE SIMULATOR!

Testing

3 circuits to test

1. Standard feedback constant current driver - no compensation nor common emitter output
2. Compensated feedback - as above but with an RC in the feedback network
3. CE output stage - standard feedback with a CE output stage

The shunt resistance will be the same in each design: 1OHM.

Each circuit will be test 10uS rise time stepped input first for 2.5A load current and then 0.1A. So V_REF in each will be set to a max of 100mV and then 2.5V. So lets have a look at the results

Circuit 1: standard circuit

RED = Gate voltage signal
GOLD = Load Current
BLUE = inverting input / feedback
GREEN = input signal/ref

As it can be seen there is some minor overshoot on the gate voltage and this also shows on the load current. So it'll overshoot by about 100mA and takes about 15uS to settle. Now lets look at 100mA:

Dear god! Well that's serious overshoot if ever I saw it! Clears the set point by 60mA (160%)! not good!

Lets see if circuit 2 is any better?

Circuit 2: compensated feedback

RED = Gate voltage signal
GOLD = Load Current
BLUE = inverting input / feedback
GREEN = input signal/ref

Really not that much difference at 2.5A, least not that I can notice.
100mA?

 Same as circuit 1 again. it doesn't seem to do much for the transient response anyway - might be doing something wrong here

Circuit 3: CE output of op-amp

 S when compared to the other 2 you can see the Gate voltage lags a bit behind the reference signal, however the overshoot seems to be lower and the settling time seems faster.

I didn't do a 100mA transient response cos I did some playing about and reduced the value of  R4 down to about 100R and repeated the above response.

The overshoot is much lower than R4=10k and settles much quicker. The gate signal still lags by a couple of uS but its not worth complaining! Here's the best bit at 100mA transient:

Wow! Compared to the other 2 that is pretty good! Very little overshoot and fast settling! I think we have a winner!

Conclusions

So why does this work - well I haven't done much research, but it looks like larger current gain by employing Q3, essentially making Q1 & Q3 a hybrid BJT-FET Darlington pair.

If I remember my control systems correctly, larger gain = faster response/sensitivity (https://en.wikipedia.org/wiki/Control_system#Proportional_control - paragraph 2) - which rings true with the vastly improved overshoot we see.

Edit: I have recently been corrected above: the output impedance from the CE stage coupled with the gate capacitance, forms a 1st order low pass filter that has better phase response than that of just the op-amp output connected to the gate - lower resistance - lower phase shift - better loop response. I'd like to simulate this effect and post it up later.

So I guess then I'll be doing a new schematic for this project then. But on top of this improvement, some more additions:

1. use 4 of these circuits in parallel to sink more current. Each shunt resistor will be a 1OHM 7W ceramic resistor. This means I can sink 2.5A per channel, meaning a total current of 10A! Mega!
2. Cos each channel is now 2.5A I can change my reference voltage to 2.5V, and guess what, I have some AD680 voltage references in DIP-8. Really good tempco on them!

So I now have a more precise, and better performing design, that exceeds spec! the max power I worked out to be about 68W, which is still ok, but not an improvement over the first design!

So I have a max rating for my design: 30V, 10A, 68W - so long as any of these are not exceeded, it should work.

The Down side: the only thing I can see is I have to employ another op-amp to do the current control, but meh, its not too difficult!